The present invention relates to timing adjustments, and more particularly to composite video timing adjustments using digital resampling.
Sub-pixel timing adjustment capability is a common requirement in video processing equipment which is synchronized, or genlocked, to a video plant timing reference, such as "black burst." Offsets, generated either by analog or digital delay lines, are typically used to compensate for varying cable lengths which distribute the video signal throughout the video plant. The routing distances, and therefore the time delay of the video signal, vary throughout the video plant, but must be time aligned when recombined. Sub-pixel timing adjustment satisfies this timing requirement. Integral pixel timing adjustments typically are used to compensate for delay introduced by digital video processing equipment, which introduce delays in multiples of a digital video clock period, present in other video plant channels.
The current state of the art for sub-pixel digital video waveform timing offsets is to use a number of "D" flip-flop registers to pipeline the digital video signal, where a series of cascaded clocks feed these registers. The cascaded clocks are buffered by some type of voltage or current controllable analog delay element. The controlling voltage or current originates from a digital to analog converter (DAC), allowing the delay to be digitally controlled. Numerous methods for implementing the delay are commercially available including those that use a triggered ramp/comparator type of vernier such as the Analog Devices AD9500, that use variable delay logic gates such as the Brooktree Bt622, and that use voltage variable capacitors (varactors) as the programmable delay element such as variable group delay, buffered, LC filter chains. Because of intrinsic propagation delays and setup/hold requirements in the registers and clock verniers, all of these methods require a minimum of two stages, and typically three stages, to implement sub-pixel delay which overlaps a full clock period. Because of the overlapping, monotonicity in crossing clock period boundaries and continuity in interacting with the integer pixel timing offset block requires at a minimum extensive calibration, and may be impossible to achieve. In addition these clock buffers, because of their analog nature, add jitter to the clock. This jitter increases in intensity with each additional pipeline stage. Clock jitter ultimately causes added distortion and noise in the digital to analog conversion process.
What is desired is a composite video timing adjustment method which is more precise than these prior methods and uses only a single, non-delayed master clock.